Power Grid Noise in TSV-Based 3-D Integrated Systems
نویسندگان
چکیده
A 3-D test circuit examining power grid noise in a 3-D integrated stack has been designed, fabricated, and tested. Fabrication and vertical bonding were performed by MIT Lincoln Laboratory for a 150 nm, three metal layer SOI process. Three wafers are vertically bonded to form a 3-D stack. Noise analysis of a power delivery topology is described. The effect of the through silicon via (TSV) density on the noise profile of a 3-D power delivery network is also discussed.
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